1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device.
2. Related Art
In formation of 45 nm node-level fine transistors, a process for doping extension impurities and/or an another activation heat process are often performed after a doping of a source drain impurity and activation heat process for inhibiting a short-channel effect. This is because higher temperature for the activation heat process with the source drain impurity causes a non-negligible diffusion of the extension impurity. A process for performing a formation of an extension after forming such source-drain involves forming a dummy side wall with a silicon nitride film, doping and activating a source drain impurity, and then removing the silicon nitride film by an etch process with phosphoric acid.
When the silicon nitride film serving as the dummy side wall is removed by an etching with phosphoric acid, only a chemically oxidized film having a thickness of about 1 nm formed during a preceding cleaning operation is present on a gate polysilicon electrode and on a portion of a substrate corresponding to a source-drain region, serving as an exposed surface of silicon. Thus, particularly in a case of a target etch removal for silicon nitride film of several tens nanometer, the chemically oxidized film could often be completely removed in some etch process due to a selectivity for silicon nitride film/oxide film, resulting in that phosphoric acid is directly in contact with the surfaces of the silicon substrate and gate polysilicon electrodes. Since phosphoric acid has a property of etching silicon, a silicon substrate or a gate polysilicon electrode is etched as a consequence. Hereinafter such phenomenon of unwanted etching is referred to as “substrate-dug”. Influences of such substrate-dug for a silicon substrate are particularly serious, and once such substrate-dug is caused in a source-drain region, an issue of increasing a junction leakage due to a decreased distance between a silicide and a junction may be caused.
On the other hand, a processing for forming a gate electrode in a 45 nm node-level fine transistor is often performed by employing a hard mask of a silicon nitride film or the like. The process employing a hard mask is more preferable than a process employing a resist mask, because a process employing a resist mask for such fine transistor, which has an extremely small gate length (dimension of electrode in a direction toward a drain from a source: L-dimension), may cause a disappearance or a deform of the gate electrode, deteriorating a processing geometry. A process of removing with phosphoric acid after the gate electrode is processed is required if a hard mask of a silicon nitride film is employed, and in such case, a similar problem as caused in the above-described removal of the dummy side wall is also caused. More specifically, the silicon substrate and/or the gate polysilicon electrode are etched. In such case, even if a substrate-dug is caused just after the gate electrode is processed, such process provides a geometry, in which the level of the surface of the source-drain region is lower than the level of the interface between the gate insulating film and the substrate, causing a deeper junction depth eventually formed therein, decreasing a minimum gate length (Lmin), which provides a tolerance for a threshold voltage (Vth) in an operation of a transistor. More specifically, minimum gate length (Lmin) is a maximum value of gate length (L dimension), which provides a slope of a plot in a graph having ordinate of threshold voltage (Vth) of transistor and abscissa of gate length (L) of not smaller than a predetermined allowed value (for example, 10 V/μm), and a transistor having smaller Lmin achieves an operation in finer region.
Typical conventional technology for solving the above-described issue is disclosed in Japanese Patent Laid-Open No. H07-211,690 (1995), in which a process for removing a silicon nitride film in a formation of an element isolation while forming an oxide film on an exposed surface of silicon by employing a hydrogen peroxide water containing phosphoric acid. In addition, Japanese Patent Laid-Open No. 2003-258,248 disclose a process as shown in FIG. 12, in which a dummy side wall 22 is once formed and then a source-drain region 23 is formed, and thereafter the dummy side wall 22 is removed to expand the source-drain region 23. For this, the dummy side wall 22 is removed after forming a protective oxide film 38 on principal surfaces of the gate electrode 21 and the source-drain region 23.
However, the above-described processes leave much to be improved. Since the removal of the silicon nitride film and the formation of the oxide film on the exposed surface of silicon are simultaneously carried out in the process described in Japanese Patent Laid-Open No. H07-211,690, it is impossible to form a chemically oxidized film having sufficient quality for preventing the substrate-dug with phosphoric acid. Thus, it is difficult to obtain a semiconductor device having a desired geometry.
On the other hand, the process described in Japanese Patent Laid-Open No. 2003-258,248 includes that, in the formation of a protective oxide film on the source-drain region of on the gate electrode, the oxide film is formed by a dry process. However, a thermal processing such as the dry oxidization described therein generally causes a deeper junction depth in the source-drain region due to a diffusion of an impurity, and on the other hand an impurity causes redistributing in the gate polysilicon electrode, migrating through the gate insulating film, thereby causing inhomogeneous channel impurity concentration, and therefore it is difficult to obtain a desired electrical characteristic by such process.